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DG535/536
Vishay Siliconix
16-Channel Wideband Video Multiplexers
DESCRIPTION
The DG535/536 are 16-channel multiplexers designed for routing one of 16 wideband analog or digital input signals to a single output. They feature low input and output capacitance, low on-resistance, and n-channel DMOS "T" switches, resulting in wide bandwidth, low crosstalk and high "off" isolation. In the on state, the switches pass signals in either direction, allowing them to be used as multiplexers or as demultiplexers. On-chip address latches and decode logic simplify microprocessor interface. Chip Select and Enable inputs simplify addressing in large matrices. Single-supply operation and a low 75 W power consumption vastly reduces power supply requirements. Theses devices are built on a proprietary D/CMOS process which creates low-capacitance DMOS FETs and high-speed, low-power CMOS logic on the same substrate. For more information please refer to Vishay Siliconix Application Note AN501 (FaxBack document number 70608).
FEATURES
* * * * * * * Crosstalk: - 100 dB at 5 MHz 300 MHz Bandwidth Low Input and Output Capacitance Low Power: 75 W Low rDS(on): 50 On-Board Address Latches Disable Output
Pb-free Available
RoHS*
COMPLIANT
BENEFITS
* * * * * High Video Quality Reduced Insertion Loss Reduced Input Buffer Requirements Minimizes Power Consumption Simplifies Bus Interface
APPLICATIONS
* * * * * * Video Switching/Routing High Speed Data Routing RF Signal Multiplexing Precision Data Acquisition Crosspoint Arrays FLIR Systems
FUNCTIONAL BLOCK DIAGRAM AND PIN CONFIGURATION
GND S8 S7 S6 S5 S4 S3 S2 S1 DIS CS CS EN A0 1 2 3 4 5 6 7 8 9 10 11 12 Latches/Decoders/Drivers 13 14 Top View Dual-In-Line Top View 16 15 A2 A1
DG535
DG536
28 27 26 25 24 23 22 21 20 19 18 17 S9 GND GND S1 S10 S11 S12 DIS S13 S14 S15 S16 D V+ ST A3 18 19 20 21 22 23 24 25 26 27 28 S 16 GND S 15 GND S 14 GND S 13 GND S 12 GND GND CS CS EN A0 A1 A2 A3 ST V+ D 7 8 9 10 11 12 13 14 15 16 17 Latches/ Decoders/ Drivers 39 38 37 36 35 34 33 32 31 30 29 S6 GND S7 GND S8 GND S9 GND S10 GND S11 PLCC/Cerquad GND GND S4 GND S5 GND S2 S3
65432
1 44 43 42 41 40
* Pb containing terminations are not RoHS compliant, exemptions may apply Document Number: 70070 S-71241-Rev. E, 25-Jun-07 www.vishay.com 1
DG535/536
Vishay Siliconix
ORDERING INFORMATION
Temperature Range Package 28-Pin Plastic DIP - 40 to 85 C 44-Pin PLCC Part Number DG535DJ DG535DJ-E3 DG536DN DG536DN-E3
TRUTH TABLE
EN 0 X X CS X 0 X CS X X 1 STa 1 A3 X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 X A2 X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 X A1 X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 X A0 X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 X Channel Selected None S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 Maintains previous switch condition Disableb High Z
1
1
0
1
Low Z
X X X Logic "0" = VAL 4.5 V Logic "1" = VAH 10.5 V X = Do not Care
0
High Z or Low Z
Notes: a. Strobe input (ST) is level triggered. b. Low Z, High Z = impedance of Disable Output to GND. Disable output sinks current when any channel is selected.
ABSOLUTE MAXIMUM RATINGS
Parameter V+ to GND Digital Inputs VS, VD Current (any terminal) Continuous Current (S or D) Pulsed 1 ms 10 % duty cycle (A Suffix) Storage Temperature (D Suffix) Power Dissipation (Package)a 28-Pin Plastic DIPb 28-Pin Sidebrazec 44-Pin PLCCd 44-Pin Cerquade Limit - 0.3 to + 18 (GND - 0.3) to (V+) + 2 or 20 mA, whichever occurs first (GND - 0.3) to (V+) + 2 or 20 mA, whichever occurs first 20 40 - 65 to 150 - 65 to 125 625 1200 450 825 Unit
V
mA C
mW
Notes: a. All leads soldered or welded to PC board. b. Derate 8.6 mW/C above 75 C. c. Derate 16 mW/C above 75 C. d. Derate 6 mW/C above 75 C. e. Derate 11 mW/C above 75 C.
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Document Number: 70070 S-71241-Rev. E, 25-Jun-07
DG535/536
Vishay Siliconix
SPECIFICATIONSa
Test Conditions Unless Otherwise Specified V+ = 15 V, ST, CS = 10.5 V Parameter Analog Switch Analog Signal Rangee Drain-Source On-Resistance Resistance Match Source Off Leakage Current Drain On Leakage Current Disable Output Digital Control Input Voltage High Input Voltage Low Address Input Current Address Input Capacitance Dynamic Characteristics PLCC On State Input Capacitance
e
A Suffix - 55 to 125 C Tempb Full Typc Minc 0 55 Maxc 10 90 120 9 10 100 10 1000 200 250
D Suffix - 40 to 85 C Minc 0 Maxc 10 90 120 9 10 100 - 10 - 100 200 250 Unit V
Symbol VANALOG rDS(on) rDS(on) IS(off) ID(on) RDISABLE VAIH VAIL IAI CA
CS = 4.5 V, VA = 4.5 or 10.5 Vf
IS = - 1 mA, VD = 3 V, EN = 10.5 V Sequence Each Switch On VS = 3 V, VD = 0 V, EN = 4.5 V VS = VD = 3 V, EN = 10.5 V IDISABLE = 1 mA, EN = 10.5 V
Room Full Room Room Full Room Full Room Full Full Full Room Full Full Room Room Room Room Room Room Room Room Room Full Full Full Full Room
- 10 - 100 - 10 - 1000 100
- 10 - 100 - 10 - 100
nA
10.5 < 0.01 5 32 35 40 2 5 3 8 12 9 300 25 300 150 - 35 - 100 - 93 - 60 - 85 - 84 - 60 - 92 - 87 - 72 - 74 - 74 - 60 500 - 60 20 55 8 45 -1 - 100 4.5 1 100
10.5 -1 - 100 4.5 1 100
V A pF
VA = GND or V+
45 55 8 pF 20
CS(on)
VD = V S = 3 V
Cerquad DIP PLCC
Off State Input Capacitancee
CS(off)
VS = 3 V
Cerquad DIP PLCC
Off State Output Capacitancee Multiplexer Switching Time Break-Before-Make Interval EN, CS, CS, ST, tON EN, CS, CS, ST, tOFF Charge Injection Single-Channel Crosstalk
CD(off) tTRANS tOPEN tON tOFF Q XTALK(SC)
VD = 3 V
Cerquad DIP
See Figure 4 See Figure 2 and 3 See Figure 2 See Figure 5 RIN = 75 , RL = 75 f = 5 MHz See Figure 9 RIN = RL = 75 , f = 5 MHz EN = 4.5 V See Figure 8 RIN = 10 , RL = 10 k f = 5 MHz See Figure 10 RIN = 10 , RL = 10 k f = 5 MHz See Figure 7 PLCC Cerquad DIP PLCC Cerquad DIP PLCC Cerquad DIP PLCC Cerquad DIP
300 25 300 150 pC ns
Room Room Room Room Room Room Room Room Room Room Room Room Room
Chip Disabled Crosstalk
XTALK(CD)
dB
Adjacent Input Crosstalk
XTALK(AI)
- 60
All Hostile Crosstalke Bandwidth
XTALK(AH) BW
RL = 50 , See Figure 6
MHz
Document Number: 70070 S-71241-Rev. E, 25-Jun-07
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DG535/536
Vishay Siliconix
SPECIFICATIONSa
Test Conditions Unless Otherwise Specified V+ = 15 V, ST, CS = 10.5 V Parameter Power Supplies Positive Supply Current Supply Voltage Range Symbol CS = 4.5 V, VA = 4.5 or 10.5 Vf Tempb Room Full Full Full Full See Figure 1 Full 50 50 Typc 5 10 200 100 A Suffix - 55 to 125 C Minc Maxc 50 100 16.5 D Suffix - 40 to 85 C Minc Maxc 50 100 16.5 Unit
I+ V+
Any One Channge I Selected with All Logic Inputs at GND or V+
A V
10 200 100
Minimum Input Timing Requirements tSW Strobe Pulse Width A0, A1, A2, A3 CS, CS, EN Data Valid to Strobe A0, A1, A2, A3 CS, CS, EN Data Valid after Strobe tDW tWD
ns
Notes: a. Refer to PROCESS OPTION FLOWCHART. b. Room = 25 C, Full = as determined by the operating temperature suffix. c. Typical values are for DESIGN AID ONLY, not guaranteed nor subject to production testing. d. The algebraic convention whereby the most negative value is a minimum and the most positive a maximum, is used in this data sheet. e. Guaranteed by design, not subject to production test. f. VA = input voltage to perform proper function.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
TYPICAL CHARACTERISTICS 25 C, unless otherwise noted
400 r DS(on) - Drain-Source On-Resistance () r DS(on) - Drain-Source On-Resistance () 360 320 280 240 200 160 120 80 40 0 0 2 4 6 8 10 VD - Drain Voltage (V) - 55 C 25 C 125 C V+ = +15 V GND = 0 V 300 270 240 210 180 12 V 150 120 90 60 30 0 0 2 4 6 8 10 VD - Drain Voltage (V) 15 V 8V GND = 0 V TA = 25 C
rDS(on) vs. VD and Temperature
rDS(on) vs. VD and Power Supply Voltage
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Document Number: 70070 S-71241-Rev. E, 25-Jun-07
DG535/536
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 C, unless otherwise noted
10 9 8 7 V th (V) 6 I+ (A) 5 4 3 2 2 1 0 8 10 12 14 16 18 V+ - Positive Supply (V) 0 10 11 12 13 14 15 16 17 18 V+ - Positive Supply (V) GND = 0 V TA = 25 C 14 12 10 125 C 8 25 C 6 4 - 55 C GND = 0 V
Logic Input Switching Threshold vs. Supply Voltage (V+)
1 A 100 nA V+ = + 15 V GND = 0 V VD = V S = 3 V I S, I D - Leakage 1 A 100 nA
Supply Current vs. Supply Voltage and Temperature
V+ = + 15 V GND = 0 V ID(off) IS(off)
I D(on) - Leakage
10 nA
10 nA
1 nA
1 nA
100 pA
100 pA
10 pA
10 pA
1 pA - 55 - 35 - 15 5 25 45 65 85 105 125
1 pA - 55 - 35 - 15 5 25 45 65 85 105 125 Temperature (C) Temperature (C)
ID(on) vs. Temperature
- 120 DG536 RIN = 10 -4 0
Leakage Current vs. Temperature
- 100
DG536 X TALK(AI) (dB) - 80 DG536 RIN = 75 Insertion Loss (dB) -8 - 3 dB Points - 12 Test Circuit See Figure 6 RL = 50
- 60 DG535 RIN = 10
- 40
- 16 - 20 Test Circuit See Figure 10 - 20 0.1 1 10 100 1
DG535
0 f - Frequency (MHz)
10
100
1000
f - Frequency (MHz)
Adjacent Input Crosstalk vs. Frequency
- 3 dB Bandwidth Insertion Loss vs. Frequency
Document Number: 70070 S-71241-Rev. E, 25-Jun-07
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DG535/536
Vishay Siliconix
TYPICAL CHARACTERISTICS 25 C, unless otherwise noted
- 160 - 140 - 120 X TALK(CD) (dB) X TALK(AH) (dB) - 100 - 80 - 60 - 40 - 20 0 0.1 1 10 100 f - Frequency (MHz) DG535 RL = 75 Test Circuit See Figure 8 - 160 - 140 - 120 - 100 - 80 - 60 - 40 - 20 0 0.1 1 10 100 f - Frequency (MHz) DG535 RIN = 10 RL = 10 k Test Circuit See Figure 7 DG536 RIN = 10 RL = 10 k DG536 RIN = 75 RL = 75
DG536 RL = 75
DG536 RL = 50
Chip Disable Crosstalk vs. Frequency
- 160 Test Circuit See Figures 2, 3, 4 - 140 tON - 120 X TALK(SC) (dB) - 100
All Hostile Crosstalk vs. Frequency
160 140 120 Switching Time (ns) 100 80 60 40 20 0 - 55 - 35 - 15 5 25 45 65 85 105 125 Temperature (C) tOFF
Test Circuit See Figure 9 RIN = 75 RL = 75
tBBM
DG536 - 80 - 60 DG535 - 40 - 20 0 0.1 1 10 100 f - Frequency (MHz)
tON, tOFF and Break-Before-Make vs. Temperature
Single Channel Crosstalk vs. Frequency
INPUT TIMING REQUIREMENTS
15 V ST 0V tSW tDW 15 V 10.5 V CS, A0, A1, A2, A3 CS, EN 4.5 V 0V 4.5 V 10.5 V tWD 7.5 V
Figure 1.
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Document Number: 70070 S-71241-Rev. E, 25-Jun-07
DG535/536
Vishay Siliconix
TEST CIRCUITS
+ 15 V
+ 15 V
Logic Input
ST A0 A1 A2 A3
V+ S16 S1 - S15 +3V
Address Logic Input tr < 20 ns tf < 20 ns
CS 15 V 50 % 0V EN or CS
90 % D 1 k 35 pF VO Signal Output
EN or CS CS GND
tON
tOFF
Figure 2. EN, CS, CS, Turn On/Off Time
+ 15 V
+ 15 V
V+ EN, CS A1, A2, A3 Address Input Logic Input A0 ST GND CS
Address Logic Input tr < 20 ns tf < 20 ns S1 +3V
15 V 0V 15 V 0V
50 %
S2 - S15
D 1 k 35 pF
VO
VOUT
tON(ST) 90 %
0V
Figure 3. Strobe ST Turn On Time
+ 15 V
+ 15 V
+3V Address Logic Input tr < 20 ns tf < 20 ns 15 V 50 % 0V Switch Output S1 Turning Off D VO tBBM 1 k 35 pF tTRANS 90 % S16 Turning On
V+ EN CS ST A0 A1 A2 A3 S1 S16 S2 thru S15
GND
CS
Figure 4. Transition Time and Break-Before-Make Interval
Document Number: 70070 S-71241-Rev. E, 25-Jun-07
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DG535/536
Vishay Siliconix
TEST CIRCUITS
+ 15 V + 15 V V+ A0, A1, A2, A3 S16 CS GND CS V+ S2 thru S15 ST EN +3V Logic Input D VO CL 1000 pF + 15 V
+ 15 V
+ 15 V
EN CS ST CS S1 Signal Generator (75 )
D A0 to A3 RL 50 W
VO
VOUT
VOUT
GND
CS
VOUT is the measured voltage error due to charge injection. The charge injection in Coulombs is Q = CL x V OUT
Figure 5. Charge Injection
Figure 6. Bandwidth
Channel 1 On S1 S2 RIN S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 V VO X TALK(AH) = 20 log 10 V RL VO S1 S2 S3 S4 S5 S6 S7 S8 S9 S10 S11 S12 S13 S14 S15 S16 V
All Channels Off
VO
RL
VO X TALK(CD) = 20 log10 V
Figure 7. All Hostile Crosstalk
Figure 8. Chip Disabled Crosstalk
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Document Number: 70070 S-71241-Rev. E, 25-Jun-07
DG535/536
Vishay Siliconix
TEST CIRCUITS
Channel 1 On S1 S2 RIN S3 S4 S5 S6 S7 S8 S9 S10 V S11 S12 S13 S14 S15 S16 Notes: 1. Any individual channel between S2 and S16 can be selected 2. X TALK(SC) = 20 log10 VO V is scanned sequentially from S 2 to S 16 X TALK(AI) = 20 log10 V Sn - 1 V Sn or 20 log10 V Sn + 1 V Sn VSn+1 RIN 10 Sn+1 RL 10 k RL VSn Sn VO RIN 10
VSn-1 Sn-1
Figure 9. Single Channel Crosstalk
Figure 10. Adjacent Input Crosstalk
PIN DESCRIPTION
Symbol S1 thru S16 D DIS CS, CS, EN A0 thru A3 ST V+ GND Analog inputs/outputs Multiplexer output/demultiplexer input Open drain low impedance to analog ground when any channel is selected Logic inputs to selected desired multiplexer(s) when using several multiplexers in a system Binary address inputs to determine which channel is selected Strobe input that latches A0, A1, A2, A3, CS, CS, EN Positive supply voltage input Analog signal ground and most negative potential All ground pins should be connected externally to ensure dynamic performance Description
Document Number: 70070 S-71241-Rev. E, 25-Jun-07
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DG535/536
Vishay Siliconix
DETAILED DESCRIPTION
The DG535/536 are 16-channel single-ended multiplexers with on-chip address logic and control latches. The multiplexer connects one of sixteen inputs (S1, S2 through S16) to a common output (D) under the control of a 4-bit binary address (A0 to A3). The specific input channel selected for each address is given in the Truth Table. All four address inputs have on-chip data latches which are controlled by the Strobe (ST) input. These latches are transparent when Strobe is high but they maintain the chosen address when Strobe goes low. To facilitate easy microprocessor control in large matrices a choice of three independent logic inputs (EN, CS and CS) are provided on chip. These inputs are gated together (see Figure 11) and only when EN = CS = 1 and CS = 0 can an output switch be selected. This necessary logic condition is then latched-in when Strobe (ST) goes low.
Signal IN
SW1
SW3
Signal OUT
SW2
Signal GND
Figure 12. "T" Switch Arrangement
The two second level series switches further improve crosstalk and help to minimize output capacitance. The DIS output can be used to signal external circuitry. DIS is a high impedance to GND when no channel is selected and a low impedance to GND when any one channel is selected. The DG535/536 have extensive applications where any high frequency video or digital signals are switched or routed. Exceptional crosstalk and bandwidth performance is achieved by using n-channel DMOS FETs for the "T" and series switches.
CS Latch A0 Latch A1 Latch A2 Latch A3 Latch ST n+ p pSubstrate GND n+ Decode Logic
CS
EN
Gate Source
Drain
Figure 11. CS, CS, EN, ST Control Logic
Break-before-make switching prevents momentary shorting when changing from one input to another. The devices feature a two-level switch arrangement whereby two banks of eight switches (first level) are connected via two series switches (second level) to a common DRAIN output. In order to improve crosstalk all sixteen first level switches are configured as "T" switches (see Figure 12). With this method SW2 operates out of phase with SW1 and SW3. In the on condition SW1 and SW3 are closed with SW2 open whereas in the off condition SW1 and SW3 are open and SW2 closed. In the off condition the input to SW3 is effectively the isolation leakage of SW1 working into the on-resistance of SW2 (typically 200 ).
Figure 13. Cross-Section of a Single DMOS Switch
It can clearly be seen from Figure 13 that there exists a PN junction between the substrate and the drain/source terminals. Should a signal which is negative with respect to the substrate (GND pin) be connected to a source or drain terminal, then the PN junction will become forward biased and current will flow between the signal source and GND. This effective shorting of the signal source to GND will not necessarily cause any damage to the device, provided that the total current flowing is less than the maximum rating, (i.e., 20 mA).
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Document Number: 70070 S-71241-Rev. E, 25-Jun-07
DG535/536
Vishay Siliconix
DETAILED DESCRIPTION
Since no PN junctions exist between the signal path and V+, positive overvoltages are not a problem, unless the breakdown voltage of the DMOS drain terminal (see Figure 13) (+ 18 V) is exceeded. Positive overvoltage conditions must not exceed + 18 V with respect to the GND pin. If this condition is possible (e.g. transients in the signal), then a diode or Zener clamp may be used to prevent breakdown. The overvoltage conditions described may exist if the supplies are collapsed while a signal is present on the inputs. If this condition is unavoidable, then the necessary steps outlined above should be taken to protect the device DC Biasing To avoid negative overvoltage conditions and subsequent distortion of ac analog signals, dc biasing may be necessary. Biasing is not required, however, in applications where signals are always positive with respect to the GND or substrate connection, or in applications involving multiplexing of low level (up to 200 mV) signals, where forward biasing of the PN substrate-source/drain terminals would not occur. Biasing can be accomplished in a number of ways, the simplest of which is a resistive potential divider and a few dc blocking capacitors as shown in Figure 14.
Analog Signal IN S V+ Analog Signal OUT
An alternative method is to offset the supply voltages (see Figure 15). Decoupling would have to be applied to the negative supply to ensure that the substrate is well referenced to signal ground. Again the capacitors should be of a type offering good high frequency characteristics. Level shifting of the logic signals may be necessary using this offset supply arrangement.
+ 12 V
DG536
GND
D
Decoupling Capacitors
+
-3V
Figure 15. DG536 with Offset Supply
TTL to CMOS level shifting is easily obtained by using a MC14504B. Circuit Layout Good circuit board layout and extensive shielding is essential for optimizing the high frequency performance of the DG536. Stray capacitances on the PC board and/or connecting leads will considerably degrade the ac performance. Hence, signal paths must be kept as short as practically possible, with extensive ground planes separating signal tracks.
+ 15 V
Analog Signal IN
C1 +
R1 S R2 V+ + C2 D Analog Signal OUT
100 F/16 V Tantalum
DG536
GND
100 F/16 V Tantalum
Figure 14. Simple Bias Circuit
R1 and R2 are chosen to suit the appropriate biasing requirements. For video applications, approximately 3 V of bias is required for optimal differential gain and phase performance. Capacitor C1 blocks the dc bias voltage from being coupled back to the analog signal source and C2 blocks the dc bias from the output signal. Both C1 and C2 should be tantalum or ceramic disc type capacitors in order to operate efficiently at high frequencies. Active bias circuits are recommended if rapid switching time between channels is required.
Vishay Siliconix maintains worldwide manufacturing capability. Products may be manufactured at one of several qualified locations. Reliability data for Silicon Technology and Package Reliability represent a composite of all qualified locations. For related documents such as package/tape drawings, part marking, and reliability data, see http://www.vishay.com/ppg?70070.
Document Number: 70070 S-71241-Rev. E, 25-Jun-07
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Legal Disclaimer Notice
Vishay
Disclaimer
All product specifications and data are subject to change without notice. Vishay Intertechnology, Inc., its affiliates, agents, and employees, and all persons acting on its or their behalf (collectively, "Vishay"), disclaim any and all liability for any errors, inaccuracies or incompleteness contained herein or in any other disclosure relating to any product. Vishay disclaims any and all liability arising out of the use or application of any product described herein or of any information provided herein to the maximum extent permitted by law. The product specifications do not expand or otherwise modify Vishay's terms and conditions of purchase, including but not limited to the warranty expressed therein, which apply to these products. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted by this document or by any conduct of Vishay. The products shown herein are not designed for use in medical, life-saving, or life-sustaining applications unless otherwise expressly indicated. Customers using or selling Vishay products not expressly indicated for use in such applications do so entirely at their own risk and agree to fully indemnify Vishay for any damages arising or resulting from such use or sale. Please contact authorized Vishay personnel to obtain written terms and conditions regarding products designed for such applications. Product names and markings noted herein may be trademarks of their respective owners.
Document Number: 91000 Revision: 18-Jul-08
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